Ham Radio 2000 #1

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Assembly Source File | 1987-05-26 | 7.5 KB | 339 lines

title "TNC1 TONE CALIBRATOR" * Tone calibration helper program for the TAPR TNC1 * Written by Marc Kaufman, WB6ECE * March 1987 * How to use this program: * * Load it using the TNCBUG boot loader. * Set the TNC jumpers as follows - * * Remove JP1 (use it for JP2 or JP3) * Install JP2 - for measurement of FSK output tones * or Install JP3 - for measurement of receive center tone * * Type 'G' to start program. * The program will continuously print out changing tone values, * directly in Hz. Adjust the appropriate pot * R38 - low tone * R36 - high tone * R43 - receiver center * * Typing 'T' will toggle between low and high tones (low is first) * Typing 'K' will key and un-key the transmit line. * This is for adjusting muting of the FSK output (R31) * and audio level (R33) * * Typing <carriage-return> will return to TNCBUG * Modification for Fast TNC * * This program is defaulted for the Slow 6809. * To reassemble for the Fast 6809, set the equate below to: * * fast equ 1 * * If you don't want to do that, just divide the displayed values by 2. fast equ 0 default is slow * * Hardware addresses acia equ $2010 6551 UART acchar equ acia acstat equ acia+1 accmnd equ acia+2 acctrl equ acia+3 pia equ $2020 6520 parallel output pra equ pia register A pcra equ pia+1 control A prb equ pia+2 register B pcrb equ pia+3 control B via equ $2040 6522 timer chip vorb equ via output register B vira equ via+1 input register A vora equ via+15 output register A, no handshake vddrb equ via+2 data direction register B vddra equ via+3 data direction register A vtim1cl equ via+4 low byte of timer 1 counter vtim1ch equ via+5 high byte of timer 1 counter vtim1ll equ via+6 low byte of timer 1 latch vtim1lh equ via+7 high byte of timer 1 latch vtim2l equ via+8 low byte of timer 2 vtim2h equ via+9 high byte of timer 2 vsr equ via+10 shift register vacr equ via+11 auxiliary control register vpcr equ via+12 peripheral control register vifr equ via+13 interrupt flag register vier equ via+14 interrupt enable register timrc1 equ vtim1cl both bytes of timer 1 counter timer2 equ vtim2l both bytes of timer2 * NOTE: this chip inverts Addresses and Data!!! hdlc equ $2800 WD 1933 HDLC chip hcr1 equ hdlc+7 control register 1 hcr2 equ hdlc+6 control register 2 hcr3 equ hdlc+5 control register 3 hrhr equ hdlc+4 receive holding register hthr equ hdlc+3 transmit holding register hir equ hdlc+3 interrupt register hsr equ hdlc+2 status register ram equ $0000 bank 0 ram ($0000 - $1fff) ram1 equ $4000 bank 1 ram ($4000 - $5fff) rom equ $e000 top rom ($e000 - $ffff) CR equ $0d carriage return LF equ $0a line feed * dsect org ram data starts in low ram * interrupt re-vector area: parallel to fff0-ffff igo fdb calib 0000 - program start point iswi3 rmb 2 0002 iswi2 rmb 2 0004 ifirq rmb 2 0006 iirq fdb ctime 0008 iswi rmb 2 000a inmi rmb 2 000c - last vector used ireset rmb 2 full reset stack equ $ff my stack is above debug stack org $100 local data starts at direct page 1 svint fcb 0 svchr fcb 0 dcount fcb 0 divide loop counter quot fdb 0,0 32 bit dividend / quotient div fdb 0 16 bit divisor (delta) addr fdb 0 output value oldval fdb 0 previous timer value delta fdb 0 delta timer value flag fcb 0 flag from interrupt that delta set oldtone fcb $ce vpcr flag (ca2 = 1, cb2 = 0)) oldkey fcb $ff key output (misc 0 bit) calib lda #1 dp page 1 tfr A,DP lds #stack set up program stack lda #$0b make sure acia doesn't interrupt sta accmnd lda <oldkey sta hcr1 set initial hdlc mode lda #$f0 sta vora sta vddra lda #$3f sta vorb sta vddrb make sure pb6 and pb7 are inputs lda <oldtone sta vpcr lda #$20 00 1 000 0 0 = timer modes sta vacr lda #$7f sta vier disable all interrupts lda #$80+$20 timer2 interrupt bit sta vier enable interrupt ldx #$ffff stx timrc1 initialize timer 1 free run ldx #$0100 = count of 1 because of flipped order stx timer2 restart interrupt and count cli enable 6809 interrupts clr <flag wait for count bsr test check acia, wait for flag clr <flag mon bsr test wait for flag ldd <delta std <div +delta, divisor lsra delta/2 for rounding rorb std <quot+2 ldd #$01c2 (32 * 921600 Hz) / (32 * delta) std <quot lda #17 sta <dcount divide takes 17 iterations div32 ldd <quot subd <div bcs .l1 overshoot, ignore subtraction std <quot .l1 tfr CC,A complement carry bit eora #1 tfr A,CC lda #4 set for shift ldx #quot+4 shft ldb 0,-x rolb stb 0,x deca bne shft loop through 4 bytes dec <dcount main iteration loop bne div32 ldx <quot+2 result cmpx <addr previous result beq mon no change stx <addr new value jsr echoa print it bra mon * interrupt routine * ctime lda hir clear possible hdlc interrupt lda vifr save interrupt flag value sta <svint bpl ctimex no interrupt ldd timrc1 timer 1 counter value tsta bne .l2 correct value on 8 bit overflow incb .l2 exg A,B put in hi-low order tfr D,X save value ldd <oldval get 'old' old value stx <oldval save 'new' old value subd <oldval delta-t std <delta inc <flag ldx #$1f00-fast*$1000 = count of 32 (slow) or 16 (fast) stx timer2 restart interrupt and count ctimex rti return * test - wait for flag, and answer acia commands * test ldb acstat bitb #$08 beq .l3 no character jsr arcv get character cmpb #'K' beq key cmpb #'T' beq tone cmpb #CR bne .l3 ignore all others lda #$ff turn off any keying sta hcr1 swi return to debug .l3 tst <flag beq test no flag, continue to wait rts exit on flag key lda <oldkey toggle keying flag eor a #1 sta <oldkey sta hcr1 bra .l3 tone lda <oldtone eora #$20 toggle tone bit (cb2) sta <oldtone sta vpcr bra .l3 * ASEND - send one character to acia (busy wait) * enter - character in A * asend ldb acstat bitb #$10 beq asend wait for previous character to clear sta acchar send this one rts * ACRLF - print cr,lf * acrlf lda #CR cr bsr asend lda #LF lf bra asend * OUT2H - put out hex digit (2 output bytes) * entry - address of byte in X * out2h lda 0,x+ out2ha sta <svchr bsr outhl output left digit lda <svchr bra outrl output right digit * outhl lsra output left hex digit lsra lsra lsra outrl anda #$f output right hex digit adda #'0' cmpa #'9' bls asend 0-9 adda #'A'-'9'-1 bra asend A-F * out4hs bsr out2h output 2 bytes plus space out2hs bsr out2h output 1 byte plus space outs lda #' ' bra asend out8hs bsr o4h output 4 bytes separated by spaces o4h bsr out2hs bra out2hs echoa ldd <addr print decimal value ldx #dectab table of decimal powers echol ldy 0,X examine entry beq echod done (zero) clr <svchr echoi subd 0,X bmi echoj overflow inc <svchr count bra echoi echoj addd 0,X++ restore and point to next tfr D,Y save value lda <svchr adda #'0' convert count to digit bsr asend tfr Y,D bra echol echod bra acrlf print cr-lf after dectab fdb 1000 fdb 100 fdb 10 fdb 1 fdb 0 * ARCV - wait for and read one character from acia * exit - character in A (8 bits) * character in B (masked to 7 bits and upper case) * arcv ldb acstat bitb #$08 beq arcv wait for character to arrive lda acchar tab andb #$7f cmpb #'a' blt .arcvx not alphabetic cmpb #'z' bgt .arcvx subb #'a'-'A' convert to upper case .arcvx rts end